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ds04-21382-1e fujitsu semiconductor data sheet copyright?2006 fujitsu li mited all rights reserved assp dts bi-cmos dual serial input pll frequency synthesizer MB15F63UL description MB15F63UL has a 2000 mhz pll frequency synthesizer wi th a high-speed frequency switching function based on the fractional-n pll (phase locked loop), and 600 mhz integer-n pll frequency synthesizer which enables pulse swallow operation. encased in a subminiatu re package (thin-bcc20), MB15F63UL has successfully achieved a small thin external form (bcc20 package dimensions: 3.50 mm 3.50 mm 0.60 mm). MB15F63UL is suitable for use in digital mobile communication devices such as gsm. features ? high frequency operation : 100 mhz to 1800 mhz (rf : 2.7 v vcc < 2.9 v) / 100 mhz to 2000 mhz (rf : 2.9 v vcc 3.3 v) 50 mhz to 600 mhz (if) fractional-n function : modulo 1048576 ( ? method) : fractional-n, enabling high-speed pll lock-up and low phase noise low voltage operation : vcc = 2.7 v to 3.3 v ultra low power supply current : 6.1 ma typ (rf) + 1.4 ma (if) vcc = 3.0 v, ta = + 25 c, in locking state direct power saving function : power supply current in power saving mode (controllable in external pin) 0.1 a typ (vcc = 3.0 v, ta = + 25 c) 10 a max (vcc = 3.0 v) internal automatic switch changeover circuit (changeover time selectable) bit function to update the changeover time constant-current charge pump circuit capa ble of switching control of the current value through serial data control or internal changeover circuit : for steady-state operation: 94 a for high-speed changeover: 4.5 ma (continued)
MB15F63UL 2 (continued) open-drain nmos switch that can be turned on and off from the internal changeover circuit prescaler division ratio : 2000 mhz prescale r (16/17/20/21) /600 mhz prescaler (8/9, 16/17) 29-bit shift register input control serial input 14-bit programmable reference divider : binary 6-bit 1 to 63 (rf side) / binary 14-bit swallow counter 3 to 16383 (if side) serial input programmable divider consisting of : binary 4-bit swallow counter 0 to 15 (rf side) / binary 7-bit swallow counter 0 to 127 (if side) binary 7-bit programmable counter 5 to 127 (rf side) /binary 11-bit swallow counter 3 to 2047 (if side) on-chip phase control for phase comparator built-in digital locking detector circui t to detect pll lo cking and unlocking extended operating temperature : ta = ? 40 c to + 85 c
MB15F63UL 3 pin assignments (top view) (lcc-20p-m06) osc in finif xfinif psif vccif clk data le vccr f finrf xfinrf psrf gnd l d/fout vprf dorf sw gnd doif vpif 20 19 18 17 11 8 9 10 7 6 5 4 3 2 1 16 15 14 13 12
MB15F63UL 4 pin descriptions pin no. pin name i/o descriptions 1vpif ? charge pump power supply for the if-pll 2 doif o charge pump output for the if-pll 3gnd ? ground pin 4 sw o open-drain switch pin for changing over the high-speed mode filter 5 dorf o charge pump output for the rf-pll 6vprf ? power supply for the rf-pll charge pump 7 ld/fout o lock detect signal output (ld) /phase comparator monitoring output (fout) pin. the output signal is selected by lds bit in a serial data. lds bit = ?h? : outputs fout signal/lds bit = ?l? : outputs ld signal 8psrfi power saving mode control for the rf-pll section. this pin must be set at ?l? when the power supply is started up. (open is prohibited. ) ps = ?h? : normal mode/ps = ?l? : power saving mode 9gnd ? ground pin 10 xfinrf i prescaler complimentary input pin for the rf-pll section. this pin should be grounded via a capacitor. 11 finrf i prescaler input pin for the rf-pll. connection to an external vco should be via ac coupling. 12 vccrf ? power supply pin for the rf-pll 13 le i load enable signal input pin (wit h the schmitt trigger circuit) when le is set ?h?, data in the shift regi ster is transferred to the corresponding latch according to the control bit in a serial data. 14 data i serial data input pin (with the schmitt trigger circuit) data is transferred to the corresponding latch (if-ref. counter, if-prog. counter, rf-ref. counter, rf-prog. counter) accordi ng to the control bit in a serial data. 15 clk i clock input pin for the 29-bit shift register (with the schmitt trigger circuit) one bit data is shifted into the shift register on a rising edge of the clock. 16 vccif ? power supply pin for the if-pll 17 oscin i the programmable reference divider input pi n. tcxo should be connected with an ac coupling capacitor. 18 xfinif i prescaler complimentary input for the if-pll section. this pin should be grounded via a capacitor. 19 finif i prescaler input pin for the if-pll. connection to an external vco should be ac coupling. 20 psif i power saving mode control pin for the if-p ll section. this pin must be set at ?l? when the power supply is started up. (open is prohibited.) ps bit = ?h? : normal mode/ps bit = ?l? : power saving mode
MB15F63UL 5 block diagram finif xfinif vccif gnd psif o scin finrf xfinrf v ccrf gnd psrf vpif doif data clk le ld/fou t vprf dorf sw 1 2 14 15 13 7 6 5 4 19 18 16 3 20 17 11 10 12 9 8 prescaler ( if ) 8/9, 16/17 swif psif programmable counter ( if ) 11 bit latch swallow counter ( if ) 7 bit latch reference counter ( if ) 14 bit latch prescaler ( rf ) 16/17/20/21 modulation fractional sigma delta 20 bit latch psrf programmable counter ( rf ) 7 bit latch swallow counter ( rf ) 4 bit latch reference counter ( rf ) 2 bit latch phase comparator ( if ) swif lock detect ( if ) charge pump ( if ) sw if fc if cs if ps if ldif 26-bit shift register 24 bit cn1 cn2 ld frif fpif fprf frrf selector ldrf lock detect ( rf ) charge pump ( rf ) phase comparator ( rf ) 2 bit latch psrf fcrf timer tmc,tm1-7 sw control odsw
MB15F63UL 6 absolute maximum ratings warning: semiconductor devices can be permanently dam aged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. recommended operating conditions warning: the recommended operating conditions are require d in order to ensure the normal operation of the semiconductor device. all of the device?s electric al characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max power supply voltage vcc ? 0.5 + 3.6 v vp vcc 3.6 v input voltage v i ? 0.5 vcc + 0.5 v output voltage ld/fout v o gnd vcc v do v do gnd vp v storage temperature tstg ? 55 + 125 c parameter symbol rating unit min typ max power supply voltage vcc 2.7 3.0 3.3 v vp vcc ? 3.3 v input voltage v i gnd ? vcc v operating temperature ta ? 40 ?+ 85 c
MB15F63UL 7 electrical characteristics (vcc = 2.7 v to 3.3 v, ta = ? 40 c to + 85 c) (continued) parameter symbol condition value unit min typ max power supply current icc if * 1 if-pll section ? 1.4 3.0 ma icc rf * 2 rf-pll section ? 6.1 10.0 ma power saving current ips if * 10 if-pll section ? 0.1* 9 10 a ips rf * 10 rf-pll section ? 0.1* 9 10 a operating frequency fin if * 3 fin if if-pll section 50 ? 600 mhz fin rf * 3 fin rf rf-pll section (2.7 v vcc < 2.9 v) 100 ? 1800 mhz rf-pll section (2.9 v vcc 3.3 v) 100 ? 2000 mhz oscin fosc reference counter setting value : r = 1 5 ? 20 mhz reference counter setting value : 2 r 63 5 ? 40 mhz input sensitivity fin if pfin if if-pll section 50 ? termination ? 15 ?+ 2dbm fin rf pfin rf rf-pll section 50 ? termination (fin = 200 mhz to 2000 mhz) ? 15 ?+ 2 dbm rf-pll section 50 ? termination (fin = 100 mhz to 200 mhz) ? 10 ?+ 2 input available voltage oscin v osc ? 0.5 ? 1.5 vp-p operating frequency of phase comparator f main_pd rf-pll section 0.4 ? 20 mhz ?h? level input voltage data, le, clk v ih schmitt trigger input 0.7 vcc + 0.4 ?? v ?l? level input voltage v il schmitt trigger input ?? 0.3 vcc ? 0.4 v ?h? level input voltage psif, psrf v ih ? 0.7 vcc ?? v ?l? level input voltage v il ??? 0.3 vcc v ?h? level input current data, le, clk i ih * 4 ?? 1.0 ?+ 1.0 a ?l? level input current i il * 4 ?? 1.0 ?+ 1.0 a ?h? level output voltage ld/fout v oh vcc = 3.0 v, i oh = ? 1 ma vcc ? 0.4 ?? v ?l? level output voltage v ol vcc = 3.0 v, i ol = 1 ma ?? 0.4 v
MB15F63UL 8 (vcc = 2.7 v to 3.3 v, ta = ? 40 c to + 85 c) *1 : finif = 190 mhz, fosc = 19.2 mhz, frif = 100 khz, v cc if = vpif = 3.0 v, ta = + 25 c, in locking state. *2 : finrf = 1600 mhz, fosc = 19.2 mhz, frrf = 19.2 mhz, v cc rf = vprf = 3.0 v, ta = + 25 c, in locking state. (continued) parameter symbol condition value unit min typ max ?h? level output voltage doif v doh vccif = vpif = 3.0 v, i doh = ? 0.5 ma vp ? 0.4 ?? v ?l? level output voltage v dol vccif = vpif = 3.0 v, i dol = 0.5 ma ?? 0.4 v ?h? level output voltage dorf v doh vccrf = vprf = 3.0 v, i doh = ? 0.01 ma vp ? 0.4 ?? v ?l? level output voltage v dol vccrf = vprf = 3.0 v, i dol = 0.01 ma ?? 0.4 v high impedance cutoff current doif dorf i off vcc = vp = 3.0 v, v off = 0.5 v to vcc ? 0.5 v ?? 2.5 na ?h? level output current ld/fout i oh * 4 vcc = 3.0 v ??? 1.0 ma ?l? level output current i ol vcc = 3.0 v 1.0 ?? ma ?h? level output current doif i doh * 4 vccif = vpif = 3.0 v, vdoif = vpif/2 csif = ?l?, ta = + 25 c ? 2.2 ? 1.5 ? 0.8 ma ?l? level output current i dol + 0.8 + 1.5 + 2.2 ma ?h? level output current i doh * 4 vccif = vpif = 3.0 v, vdoif = vpif/2 csif = ?h?, ta = + 25 c ? 8.2 ? 6.0 ? 4.1 ma ?l? level output current i dol + 4.1 + 6.0 + 8.2 ma ?h? level output current dorf i doh * 4 vccrf = vprf = 3.0 v, vdorf = vprf/2 in steady state (locking state) : ta = + 25 c ? 160 ? 94 ? 40 a ?l? level output current i dol + 40 + 94 + 160 a ?h? level output current i doh * 4 vccrf = vprf = 3.0 v, vdorf = vprf/2 channels in changeover : ta = + 25 c ? 6.1 ? 4.5 ? 2.4 ma ?l? level output current i dol + 2.4 + 4.5 + 6.1 ma charge pump current rate doif i dol /i doh i domt * 5 v do = vp/2 ? 3 ?% vs. vdo i dovd * 6 0.5v v do vcc ? 0.5 v ? 10 ?% vs. ta i dota * 7 ? 40 c ta + 85 c, v do = vcc/2 ? 5 ?% dorf i dol /i doh i domt * 8 v do = vp/2 ? 8.0 15.0 % open-drain output resistance for high-speed (sw) z ssh at normal mode (off) 100 ?? k ? at high-speed mode (on) ? 35 70 ?
MB15F63UL 9 (continued) *3 : ac coupling. 1000 pf capacit or is connected under the condi tion of minimum operating frequency. *4 : the symbol ? ? ? means direction of current flow. *5 : vcc = vp = 3.0 v, ta = + 25 c (||i 3 | ? |i 4 ||) / [ (|i 3 | + |i 4 |) / 2] 100 % *6 : vcc = vp = 3.0v, ta = + 25 c (i dol , i doh respectively) [ (||i 2 | ? |i 1 ||) / 2] / [ (|i 1 | + |i 2 |) / 2] 100 % *7 : vcc = vp = 3.0v, ta = + 25 c (i dol , i doh respectively) [ (||i do ( 85c ) | ? |i do ( ? 40c ) ||) / 2] / [ (|i do ( 85c ) | + |i do ( ? 40c ) |) / 2] 100 % *8 : v cc = vp = 3.0 v, ta = + 25 c (||i dol | ? |i doh ||) / [ (|i dol | + |i doh |) / 2] 100 % *9 : power supply current at ps = gnd (data, le and clk are v il = gnd and v ih = vcc setting.) *10 : power supply current at fosc = 19.2 mhz, v cc = v p = 3.0 v, ta = + 25 c, ps = gnd (data, le and clk are v il = gnd, v ih = vcc setting.) i dol i doh 0.5 v vp/2 vp vp ? 0.5 v i 1 i 2 i 3 i 4 i 2 i 1 charge pump output potential [v]
MB15F63UL 10 functional description 1. serial data input serial data is processed using the data, clock, and le pins. serial data controls the programmable reference divider and the programmable divider separately. binary serial data is entered through the data pin. one bit of data is shifted into the shift register on the rising edge of the clock. when the le signal pin is taken high, stored data is latched ac cording to the control bit data. the following table shows the shift register configurat ion and combinations of data transfer control bits. note : start data input with msb first. 2. setting data a) fractional-n synthesizer in the rf-pll section set each setting value for the fractional-n synthesiz er counter, according to the following equations. fvco rf = n total f osc r n total = p n + a + 3 + f/q f: set the numerator of fractional division with its fractional portion discarded. when value f is even-numbered as a result of the division calculation, ?1? is added to f. b) integer-n synthesizer in the if-pll section the integer-n synthesizer counter is set, according to the following equations. fvco if = n total f osc r n total = p n + a lsb destination of serial data msb 1234567891011121314151617181920212223242526272829 00 r1 if r2 if r3 if r4 if r5 if r6 if r7 if r8 if r9 if r10 if r11 if r12 if r13 if r14 if cs if sw if fc if ld s t1 t2 01 a1 if a2 if a3 if a4 if a5 if a6 if a7 if n1 if n2 if n3 if n4 if n5 if n6 if n7 if n8 if n9 if n10 if n11 if ps if 10 f1 rf f2 rf f3 rf f4 rf f5 rf f6 rf f7 rf f8 rf f9 rf f10 rf f11 rf f12 rf f13 rf f14 rf f15 rf f16 rf f17 rf f18 rf f19 rf f20 rf a1 rf a2 rf a3 rf a4 rf n1 rf n2 rf n3 rf 11 n4 rf n5 rf n6 rf n7 rf r1 rf r2 rf r3 rf r4 rf r5 rf r6 rf fc rf tm c tm 1 tm 2 tm 3 tm 4 tm 5 tm 6 tm 7 od sw ps rf sc fvco rf /fvco if : output frequency of externally connected vco n total : total number of divisions from prescaler input to phase comparator input fosc : reference oscillation frequency (oscin input frequency) r : rf side : setting value for binar y 6-bit reference counter (1 to 63) if side : setting value for binary 14 -bit reference counter (1 to 16383) p : rf side : division ratio for prescaler (16) if side : division ratio for prescaler (8, 16) n : rf side : setting value for binary 7-bit programmable counter (5 to 127) if side : setting value for binary 11-b it programmable counter (3 to 2047) a : rf side : setting value for binary 4-bit swallow counter (0 to 15) if side : setting value for binary 4- bit swallow counter (0 to 127, a < n) f : numerator of fractional di vision (0 to 1048575, f < q) q : denominator of fractional division (2 20 = 1048576)
MB15F63UL 11 c) data bit description bit name description f1rf to f20rf bits for setting the fractional numerator fo r the rf-pll (setting range: 0 to 1048575) (refer to table 1) a1rf to a4rf bits for setting the division ratio of the rf -side swallow counter (setting range: 0 to 15) (refer to table 2) n1rf to n7rf bits for setting the rf-side main count er (setting range: 5 to 127) (refer to table 3) r1rf to r6rf bits for setting the division ratio of the rf-s ide reference counter (setting range: 1 to 63) (refer to table 4) a1if to a7if bits for setting the division ratio of the if-s ide swallow counter (s etting range: 0 to 127) (refer to table 5) n1if to n11if bits for setting the if-side main count er (setting range: 3 to 2047) (refer to table 6) r1if to r14if bits for setting the division ratio of the if-si de reference counter (setting range: 3 to 16383) (refer to table 7) tmc control bit for setting speedup mode (refer to table 9) tmc_bit = ?0? disabled tmc _ bit = ?1? enabled tm1 to tm7 bits for setting the sp eedup timer (refer to table 8) psrf power saving bit for the rf-pll section fcrf phase switching bit for the rf-side phase comparator (refer to table 11) odsw control bit for the open-drain switch odsw bit = ?0? dynamic odsw bit = ?1? off fcif phase switching bit for the if-side phase comparator (refer to table 11) csif charge pump switching bit for the if-pll section csif bit = ?0? icp = 1.5ma csif bit = ?1? icp = 6.0ma swif bits for setting the division ra tio of the if-side prescaler swif = ?0? 16/17 swif = ?1? 8/9 psif power saving bit for the if-pll section lds, t1, t2 control bits for selecting monitor function (refer to table 10) sc bit for switching the order of ? sc bit = ?0? 2nd order sc bit = ?1? 3rd order dummy bit: must be fixed to ?0?
MB15F63UL 12 table 1 - fractional counter f numerator value setting setting value (f) f20 rf f19 rf f18 rf f17 rf f16 rf f15 rf f14 rf f13 rf f12 rf f11 rf f10 rf f9 rf f8 rf f7 rf f6 rf f5 rf f4 rf f3 rf f2 rf f1 rf 0 00000000000000000000 1 00000000000000000001 2 00000000000000000010 3 00000000000000000011 4 00000000000000000100 5 00000000000000000101 6 00000000000000000110 ? ? ? ? ? ? 1048574 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1048575 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 table 2 - swallow counter setting table 3 - main counter setting setting value (a) a4 rf a3 rf a2 rf a1 rf setting value (n) n7 rf n6 rf n5 rf n4 rf n3 rf n2 rf n1 rf 0 0 0 0 0 5 0000101 1 0 0 0 1 6 0000110 ? ? ? ? ? ? ? ? ? ? ? ? 14 1 1 1 0 126 1111110 15 1 1 1 1 127 1111111 table 4 - reference counter setting table 5 - swallow counter setting setting value (r) r6 rf r5 rf r4 rf r3 rf r2 rf r1 rf setting value (a) a7 if a6 if a5 if a4 if a3 if a2 if a1 if 1 000001 0 0000000 2 000010 1 0000001 ? ? ? ? ? ? ? ? ? ? ? ? 62 111110 126 1111110 63 111111 127 1111111
MB15F63UL 13 table 9 - charge pump output current setting table 6 - main counter setting setting value (n) n11 if n10 if n9 if n8 if n7 if n6 if n5 if n4 if n3 if n2 if n1 if 3 00000000011 4 00000000100 ? ? ? ? ? ? 2046 11111111110 2047 11111111111 table 7 - reference counter setting setting value (r) r14 if r13 if r12 if r11 if r10 if r9 if r8 if r7 if r6 if r5 if r4 if r3 if r2 if r1 if 3 00000000000011 4 00000000000100 ? ? ? ? ? ? 16382 1 1 1 1 1 1 1 1 1 1 1 1 1 0 16383 1 1 1 1 1 1 1 1 1 1 1 1 1 1 table 8 - speedup timer update value setting setting value tm 7 tm 6 tm 5 tm 4 tm 3 tm 2 tm 1 case) fosc = 19.2 mhz 1 0000001 3.3 ? ? ? ? ? ? ? ? ? charge pump current switching time = 64/fosc tm 126 1 1 1 1 1 1 0 420.0 unit: s 127 1 1 1 1 1 1 1 423.3 charge pump output current tmc 0.094 ma fixed 0 4.5 ma 0.094 ma switched 1
MB15F63UL 14 table 10 - ld/fout output setting * : the maximum operating frequency va ries depending on the output state of the ld/fout pin (ld output or fout output). table 11 - comparator polarity setting note : set the fc bit in accordance with the low pas s filter and vco polarity, wh en designing a pll frequency synthesizer. ld/fout lds t1 t2 maximum operating frequency [mhz]* ld output 0 ?? 1800 fout frif 1 0 0 2000 frrf 1 1 0 fpif 1 0 1 fprf 1 1 1 fc = ?1? fc = ?0? do do fp < fr h l fr < fp l h fr = fp z z vco polarity (1) (2) high v co o utput f requency hig h vco input voltage (1) (2) when vco is (1) fc : ?h? when vco is (2) fc : ?l?
MB15F63UL 15 3. power saving mode (intermittent operation) the intermittent operation allows internal circuits to operate only when required and to stop otherwise. it is designed to control the power co nsumed by the entire circuit block. howeve r, if the circuit starts operating directly from a stop state, the phase relation is undefined, even w hen the comparison frequency (fp) is the same as the reference frequency (fr) input to the phase comparator. as a result, the phase comparator generates excessive error signals, causing the problem of unlocking the pll. to solve this problem, the intermittent operation control has been implemented to control fluctuations in the lo cked frequency by performing forcible phase adjustment at the beginning of operation. operation mode the set channel and crystal oscillato r circuit are in operation and the pll performs normal operation. power save mode this mode realizes low current consum ption by stopping the circuits whic h will not cause any problem even when stopped. in this condition, the standard consumption current is 0.1 a per channel with the maximum of 10 a. at this point, do and ld are set to the same levels as when the pll was locked. t he do enters a high impedance state, and the voltage input to the voltage control oscilla tor (vco) remains the same as the voltage for operation mode (i.e. locked state) with the time constant of the low pass filter. therefore, the vco output frequency can be maintained almost at the same level as the lock frequency. notes : ? when power (vcc) is first applied, the device must be in power saving mode (external pin = l, due to the undefined serial data) . ? the serial data input after the power supply became st able, and then the power saving mode is released after completed the data input. psif ifpll psrf rfpll externalpin serialdata externalpin serialdata 0 0 power save 0 0 power save 0 1 power save 0 1 power save 1 0 power save 1 0 power save 11active11active off v cc c lk tv 1 s d ata l e p s on tps 100 n s (1) (2) (3) (1) ps = l (power saving mode) at power on (2) set serial data 1 s later after power supply remains stable (v cc 2.2 v) . (3) release power saving mode (ps : l h)
MB15F63UL 16 4. serial data input timing divide ratio is performed through a serial interf ace using the data pin, clock pin, and le pin. setting data is read into the shift register at the rise of the clock signal, and transferre d to a latch at the rise of the le signal. the following diagram shows the data input timing. d ata msb t 1 t 2 t 5 t 4 t 3 t 6 t 0 lsb c lk l e 100 ns t 0 , t 6 20 ns t 1 , t 2 , t 4 30 ns t 3 , t 5 le should be ?l? when the data is tr ansferred into the shift register. 1st. data 2nd. data control bit invalid data
MB15F63UL 17 phase comparator output waveform (fc bit = ?h?) (fc bit = ?l?) ? ld output logic notes : ? phase error detection range : ? 2 to + 2 ? pulses on do signal during locked st ate are output to prevent dead zone. rf-pll section : ? ld output becomes ?l? when phase is t wu or more. ld output becomes ?h? when phase error is t wl or less and continues to be so for ten cycles or more. ? t wu and t wl depend on fin input frequency. if-pll section ? ld output becomes ?l? when phase is t wu or more. ld output becomes ?h? when phase error is t wl or less and continues to be so for three cycles or more. ? t wu and t wl depend on oscin input frequency. if-pll section rf-pll section ld output locking state/power saving state locking state/power saving state h locking state/power saving state unlocking state l unlocking state locking state/power saving state l unlocking state unlocking state l t wu 1 / (fin / 16) [s] ex.) fin = 1629.9 mhz : t wu 9.82 ns t wl 2 / (fin / 16) [s] : t wl 19.63 ns t wu 2 / fosc [s] ex.) fosc = 13.0 mhz : t wu 153 ns t wl 4 / fosc [s] : t wl 256 ns f r rf f p rf t wu t wl l d d o rf d o rf
MB15F63UL 18 measurment circuit (for measuring input sensitivity fin/oscin) doif gnd vprf sw dorf 0.1 f psif xfinif oscin finif vpif 0.1 f MB15F63UL bump chip carrier-20 16 19 15 14 13 17 12 11 7 6 5 4 3 2 1 20 8 9 10 18 50 ? 1000 pf v cc if s.g s.g 50 ? 1000 pf v cc if le data clk v cc rf v cc rf 50 ? 1000 pf 1000 pf s.g 0.1 f finrf xfinrf gnd psrf ld / fout controller (setting divide ratio) oscilloscope
MB15F63UL 19 typical characteristics 1. fin input sensitivity ? 50 ? 45 ? 40 ? 35 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 0 5 10 spec 0 500 1000 1500 2000 2500 v cc = 3.0 v v cc = 3.3 v v cc = 2.7 v 300 0 ? 50 ? 45 ? 40 ? 35 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 0 5 10 spec 0 500 1000 v cc = 3.0 v v cc = 3.3 v v cc = 2.7 v 150 0 rf input sensitivity ? input frequency if input sensitivity ? input frequency rf input sensitivity (dbm) if input sensitivity (dbm) input frequency (mhz) input frequency (mhz)
MB15F63UL 20 2. oscin input sensitivity ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 0 5 10 0 10203040506070809010 0 v cc = 3.0 v v cc = 3.3 v v cc = 2.7 v spec oscin input sensitivity ? input frequency input frequency (mhz) oscin input sensitivity (dbm)
MB15F63UL 21 3. rf do output current 200 2.0 3.0 0.0 ? 200 0.0 1.0 v cc rf = vprf = 3.0 v 6.0 2.0 3.0 0.0 ? 6.0 0.0 1.0 v cc rf = vprf = 3.0 v ? cp = 94 a ? cp = 4.5 ma i do ? v do charge pump output current i do ( a) charge pump output voltage v do (v) i do ? v do charge pump output current i do (ma) charge pump output voltage v do (v)
MB15F63UL 22 4. if do output current 2.0 2.0 3 .0 0.0 ? 2.0 0.0 1.0 v cc if = vpif = 3.0 v 7.0 2.0 3.0 0.0 ? 7.0 0.0 1.0 v cc if = vpif = 3.0 v ? cp = 1.5 ma ? cp = 6 ma i do ? v do charge pump output current i do (ma) charge pump output voltage v do (v) i do ? v do charge pump output current i do (ma) charge pump output voltage v do (v)
MB15F63UL 23 5. fin input impedance s tart 100.000 000 mhz stop 600.000 000 mhz 4 : 6.2119 ?? 21.005 ? 12.628 pf 600.000 000 mhz 82.813 ? ? 246.07 ? 100 mh z 22.242 ? ? 117.85 ? 200 mh z 7.8457 ? ? 49.664 ? 400 mh z 1 : 2 : 3 : 1 2 3 4 1 2 3 4 s tart 100.000 000 mhz stop 2 000.000 000 mhz 4 : 12.429 ? 2.9873 ? 237.72 ph 2 000.000 000 mhz 32.969 ? ? 153.25 ? 500 mh z 17.539 ? ? 65.531 ? 1 gh z 18.783 ? ? 26.514 ? 1.5 gh z 1 : 2 : 3 : finif input impedance finrf input impedance
MB15F63UL 24 6. oscin input impedance 4.116 k ? ? 10.916 k ? 5 mh z 996 ? ? 6.3023 k ? 10 mh z 195.13 ? ? 3.0835 k ? 20 mh z 1 : 2 : 3 : s tart 5.000 000 mhz stop 20.000 000 mhz 4 : 195.13 ?? 3.0835 k ? 2.5808 p f 20.000 000 mh z 1 2 3 4
MB15F63UL 25 reference information s.g. oscin do lpf fin sw vco spectrum analyzer 10000 pf 2200 pf 0.62 k ? sw 3.6 k ? do vc o fvco = 800 mhz vcc = vp = 3.0 v kv = 25 mhz/v vvco = 5.0 v fr = 6.5 mhz (r = 2) ta = + 25 c fosc = 13.0 mhz tmc = ?1?, tm = ?4? cs = ?0?, odsw = ?0?, sc = ?1?, mode = ?0? atten 10 db vavg 20 mkr ? 88.56 db/h z 1.00 khz 10 db/ rl 0 dbm ? mkr ? 1.00 khz ? 88.56 db/hz d s center 800.00000 mhz span 10.00 khz rbw 100 hz vbw 100 hz swp 802 ms atten 10 db vavg 20 mkr ? 116.8 db/h z 200.0 khz 10 db/ rl 0 dbm ? mkr ? 200.0 khz ? 116.8 db/hz d s center 800.0000 mhz span 500.0 khz ? rbw 1.0 khz vbw 1.0 khz swp 1.30 s atten 10 db vavg 20 mkr ? 82.17 db 6.50 mhz 10 db/ rl 0 dbm ? mkr ? 6.50 mhz ? 82.17 db d s center 812.50 mhz span 15.00 mhz ? rbw 30 khz vbw 30 khz swp 50.0 ms ? pll phase noise & spurious noise c/n 1 khz offset c/n 200 khz offset ref. leakage 6.5 mhz offset
MB15F63UL 26 8 35.004000 mhz 8 35.000000 mhz 8 34.996000 mhz 0.00 s 500.0 s 100.0 s/div 1.000 ms 8 00.004000 mhz 8 00.000000 mhz 7 99.996000 mhz 0.00 s 500.0 s 100.0 s/div 1.000 ms pll lock up time l : 800 mhz h : 835 mhz 1 khz l ch h ch 373 s pll lock up time h : 835 mhz l : 800 mhz 1 khz h ch l ch 364 s
MB15F63UL 27 application example MB15F63UL bump chip carrier-20 le data clk psif v cc if xfinif vpif oscin gnd v cc rf vprf psrf xfinrf finif finrf 1000 pf sw doif dorf 18 ? 18 ? 0.1 f 0.1 f gnd ld/fout 0.1 f 18 ? tcxo lock det. lpf rf output 1000 pf lpf if 18 ? 18 ? o utput 1000 pf v cc rf 16 19 15 14 13 17 12 11 7 6 5 4 3 2 1 20 8 9 10 18 18 ? 0.1 f v cc if note : clk, data and le are the built -in schmitt trigger circuits (insert a pull-down or pull-up register to prevent oscillation when open-circuit in the input) . controller (setting divide ratio) vco, rf-pll vco, if-pll
MB15F63UL 28 precautions for use the fractional-n pll used in the rf section is based on the ? system and has the following characteristics. (1) integer operation when f = 0 when f is set to ?0?, the ? circuit block is stopped completely and the same operation as a normal integer product is performed. therefore, the most pref erable noise characteristics can be achieved. (2) generation of spurious signals 1.spurious signals are generated in the offset part of fp, which is a comparison frequency (equivalent of a reference leak in the integer type). example: if fosc is set to 13 mhz and r is set to 2 when f vco is 800 mhz in the gsm 80 0 mhz band, ntotal becomes 124 and f becomes 0. (integer mode) spurious signals are generated at ?fp / r = 13 mhz / 2 = 6.5 mhz? offset. (reference leak) (the waveform resembles that of the reference leakage shown on ref leakage of ?reference informa- tion?. a filter can be used to eliminate the effects.) 2. due to the ? circuit operation, spurious si gnals are generated where ?f / q fp? or ?(q ? f) / q fp? is located. example: fosc = 13 mhz; r = 2 in gsm 800 mhz band: when fvco is 806.2 mhz, ntotal becomes 142. 0307692... and f becomes 32263. consequently, spurious signals are generated at ?f / q fp : = 200 khz? offset. adjusting the filter may reduce these spurious signals. furthermore, modifying r a nd fr may change the setting value to avoid to generate spurious signals. for example, when fosc = 13 mhz an d r = 2, ntotal becomes 125.0307692 , where fvco is 812.7 mhz. therefore, f becomes 32263. spurious signals are supposed to be g enerated at ?f / q fp : = 200 khz? and 200 khz offset. however, if r is changed to 3, f will become 572683 and ?f / q fp : = 2.366 mhz? and spurious signals will be the outer frequencies. therefore, the effects will not be foreseen. atten 10 db vavg 20 mkr ? 82.50 db 200.0 khz 10 db/ rl 0 dbm ? mkr ? 200.0 khz ? 82.50 db d s center 806.2000 mhz span 500.0 khz ? rbw 1.0 khz ? vbw 3.0 khz swp 1.30 s c/n 200 khz offset
MB15F63UL 29 note that the problem cannot be avoided when the se tting value of the swallow counter (a) is odd-numbered (also applicable to the 806.2 mhz env ironment, used in the above explanation). however, the spurious signals can be reduced by changing fr (reducing it) to limit the band. note that in this case, the comparison frequency itself changes, resultin g in a change in the loop b and and deterioration of cn. therefore,each case should be handled in accordance with the system used. some example waveforms are attached to the following.
MB15F63UL 30 atten 10 db vavg 20 atten 10 db vavg 20 mkr ? 89.50 db 200.0 khz 10 db/ rl 0 dbm 200.0 khz 10 db/ rl 0 dbm ? mkr ? 90.83 db ? mkr ? 200.0 khz mkr ? 200.0 khz ? 89.50 db ? 90.83 db d s d s center 812.7000 mhz span 500.0 khz ? rbw 1.0 khz vbw 1.0 khz swp 1.30 s center 812.7000 mhz span 500.0 khz ? rbw 1.0 khz vbw 1.0 khz swp 1.30 s atten 10 db vavg 20 atten 10db vavg 20 mkr ? 3.00 db 12.00 khz 10 db/ rl 0 dbm 10.08 khz 10 db/ rl 0 dbm ? mkr ? 3.00 db ? mkr ? 12.00 khz mkr ? 10.08 khz ? 3.00 db ? 3.00 db d s d s center 812.70000 mhz span 50.00 khz rbw 300 hz vbw 300 hz swp 1.40 s center 812.70000 mhz span 50.00 khz rbw 300 hz vbw 300 hz swp 1.40 s atten 10db vavg 20 atten 10 db vavg 20 mkr ? 89.23 db/hz 1.00 khz 10 db/ rl 0 dbm 1.00 khz 10 db/ rl 0 dbm ? mkr ? 82.57 db/hz ? mkr ? 1.00 khz mkr ? 1.00 khz ? 89.23 db/hz ? 82.57 db/hz d s d s center 812.70000 mhz span 10.00 khz rbw 100 hz vbw 100 hz swp 802 ms center 812.70000 mhz span 10.00 khz rbw 100 hz vbw 100 hz swp 802 ms r = 2 (200 khz offset) r = 3 (200khz offset) r = 2 (loop band waveform) r = 3 (loop band waveform) r = 2 (1khz offset) r = 3 (1khz offset)
MB15F63UL 31 3. excessive spurious signals are generated when sett ing a binary division such as f/q = 1/2, 1/4, 1/8 if it is difficult to reduce the excess level, value f can be shifted to the acceptable range of frequency differences to reduce it. example: spurious noise is generated on the en tire floor when f = 524288 (f/q = 1/2). spurious noise is generated on the ent ire floor when f = 262144 (f/q = 1/4). the following section shows examples of spurious waveforms generated in the above cases as well as examples of waveforms when 5 and 10 are added to value f.
MB15F63UL 32 atten 10 db mkr ? 8.83 dbm 809.2500 mhz 10 db/ rl 0 dbm mkr 809.2500 mhz ? 8.83 dbm d s center 809.2500 mhz span 200.0 khz ? rbw 1.0 khz ? vbw 3.0 khz ? swp 500 ms atten 10db mkr ? 8.50 dbm 807.6250 mhz 10 db/ rl 0 dbm mkr 807.6250 mhz ? 8.50 dbm d s center 807.6250 mhz span 200.0 khz ? rbw 1.0 khz ? vbw 3.0 khz ? swp 500 ms atten 10 db mkr ? 8.50 dbm 809.2500 mhz 10 db/ rl 0 dbm mkr 809.2500 mhz ? 8.50 dbm d s center 809.2500 mhz span 200.0 khz ? rbw 1.0 khz ? vbw 3.0 khz swp 500 ms atten 10 db mkr ? 8.67 dbm 807.6250 mhz 10 db/ rl 0 dbm mkr 807.6250 mhz ? 8.67 dbm d s center 807.6250 mhz span 200.0 khz ? rbw 1.0 khz ? vbw 3.0 khz swp 500 ms atten 10 db mkr ? 9.17 dbm 809.2500 mhz 10 db/ rl 0 dbm mkr 809.2500 mhz ? 9.17 dbm d s center 809.2500 mhz span 200.0 khz ? rbw 1.0 khz ? vbw 3.0 khz ? swp 500 ms atten 10 db mkr ? 9.17 dbm 807.6250 mhz 10 db/ rl 0 dbm mkr 807.6250 mhz ? 9.17 dbm d s center 807.6250 mhz span 200.0 khz ? rbw 1.0 khz ? vbw 3.0 khz swp 500 ms f = 524288(f/q = 1/2) f = 262144(f/q = 1/4) f = 524288 + 5f = 262144 + 5 f = 524288 + 10 f = 262144 + 10
MB15F63UL 33 notes : ? v cc rf and v cc if must be equal voltage. even if either rf-pll or if-pll is not used, power must be supplied to v cc rf and v cc if to keep them equal. it is recommended that the non-use pll is controlled by power saving function. ? to protect against damage by electrostatic di scharge, note the following handling precautions : - store and transport devices in conductive containers. - use properly grounded workstat ions, tools, and equipment. - turn off power before inserting device into or removing device from a socket. - protect leads with a conductive sheet when transporting a board-mounted device.
MB15F63UL 34 ordering information part number package remarks MB15F63ULpva1 20-pin, plastic bcc (lcc-20p-m06)
MB15F63UL 35 package dimensions 20 -pin pla s tic bcc lead pitch 0.50 mm package width package length 3 .50 mm 3 .50 mm s ealing method pla s tic mold mounting height 0.60 mm max weight 0.01 g 20 -pin pla s tic bcc (lcc- 20 p-m0 6 ) (lcc-20p-m06) c 2004 fujit s u limited c20057 s -c-1-1 0.500.10 (.020.004) 0.50(.020) typ. 3 .500.10 (.1 38 .004) 0.550.050 (.022.0020) 0.0750.025 (.00 3 .001) ( s tand off) 0.05(.002) 7 17 1.00(.004) ref. "b" detail s of "b" part (.012.002) 0. 3 00.06 0.20(.00 8 ) index area (.1 38 .004) 3 .500.10 (.012.002) 0. 3 00.06 (.016.002) 0.400.06 detail s of "a" part 3 .00(.11 8 )ref. 0.50(.020) typ 11 0.14(.006) min 17 11 1 7 mount height 1 "a" 1pin index 1.55(.061) 0.95 (.0 3 7) 2.90(.114) typ. typ. 2.90(.114) 0.20(.00 8 ) 0.400.06 (.016.002) 1pin index dimen s ion s in mm (inche s ). note: the value s in parenthe s e s are reference value s .
MB15F63UL f0610 fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. edited business promotion dept.

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